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From: johnl@ima.UUCP (John R. Levine)
Newsgroups: net.arch
Subject: Re: Delayed Loads
Message-ID: <221@ima.UUCP>
Date: Wed, 24-Sep-86 12:06:52 EDT
Article-I.D.: ima.221
Posted: Wed Sep 24 12:06:52 1986
Date-Received: Wed, 24-Sep-86 22:25:56 EDT
References: <5100133@ccvaxa> <1174@ncr-sd.UUCP>
Reply-To: johnl@ima.UUCP (John R. Levine)
Organization: Javelin Software Corporation
Lines: 19

In article <1174@ncr-sd.UUCP> stubbs@ncr-sd.UUCP (0000-Jan Stubbs) writes:
>In article <5100133@ccvaxa> aglew@ccvaxa.UUCP writes:
>>can anybody say anything useful about delayed load/stores? Ie. memory
>>access functions that are defined to work the same way as delayed
>>branches, not to take effect until after a few more instructions.
>NCR 8500 (circa 1975) and 8600 (circa 1979)is one such machine ...

The IBM 360/91, circa 1969, had overlapped loads and stores.  The manual
suggested that if you reorder instructions so that the result register
of one instruction is not used as an operand until a few instructions later,
your program will run a lot faster.  But there was also considerable expensive
hardware so that if you did use your results immediately, it interlocked to
make the program work correctly.  The CDC 6600 had similar overlaps and
interlocks even earlier, about 1966.
-- 
John R. Levine, Javelin Software Corp., Cambridge MA +1 617 494 1400
{ ihnp4 | decvax | cbosgd | harvard | yale }!ima!johnl, Levine@YALE.EDU
The opinions expressed herein are solely those of a 12-year-old hacker
who has broken into my account and not those of any person or organization.