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From: johnl@ima.UUCP (John R. Levine)
Newsgroups: net.arch
Subject: Re: MC68030 Cache Organization
Message-ID: <237@ima.UUCP>
Date: Fri, 3-Oct-86 19:11:35 EDT
Article-I.D.: ima.237
Posted: Fri Oct  3 19:11:35 1986
Date-Received: Mon, 6-Oct-86 18:42:29 EDT
References: <5100146@ccvaxa>
Reply-To: johnl@ima.UUCP (John R. Levine)
Organization: Javelin Software Corporation
Lines: 26

In article <5100146@ccvaxa> aglew@ccvaxa.UUCP writes:
>
>Motorola 68030 Cache Organization
>---------------------------------
>
>Can someone explain to me why the change in cache organization between
>the 68020 and the 68030 is such a win? ...
>
>    To improve the likelihood of cache hits, Motorola is also reorganizing
>    the 256-byte instruction cache into 16 entries of four long words each
>    with 4 bytes per word. The 68020 instruction cache consists of 64 entries
>    each of one long word... The reorganized instruction cache, along with
>    the new burst mode addressing methods, should double the cache hit ratio
>    and reduce the number of times the 68030 must access the system bus.

According to an article in Digital Design, the big win with this kind of
cache design is that it takes advantage of nibble mode RAM chips that can
cycle four sequential bits out very fast.  It means you can get four times the
data in a bus transaction in much less than four times the time.  Since much
read access is sequential anyway (instruction execution, or scanning a string
or a table) it's a big win.
-- 
John R. Levine, Javelin Software Corp., Cambridge MA +1 617 494 1400
{ ihnp4 | decvax | cbosgd | harvard | yale }!ima!johnl, Levine@YALE.EDU
The opinions expressed herein are solely those of a 12-year-old hacker
who has broken into my account and not those of any person or organization.