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From: pauls@mips.UUCP (Paul Sweazey)
Newsgroups: net.arch
Subject: Re: Anyone got a list of references on cache memories?
Message-ID: <715@mips.UUCP>
Date: Tue, 7-Oct-86 02:13:47 EDT
Article-I.D.: mips.715
Posted: Tue Oct  7 02:13:47 1986
Date-Received: Wed, 8-Oct-86 00:43:15 EDT
References: <7093@boring.mcvax.UUCP>
Organization: MIPS Computer Systems, Sunnyvale, CA
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> Does anyone out there have a list of references to articles on
> cache memories that they wouldn't mind sharing?

Alan Jay Smith of UC Berkeley compiled an extremely comprehensive
"Bibliography and Readings on CPU Cache Memories and Related Topics",
found in the Vol. 14, No. 1, January 1986 issue of Computer Architecture
News, an informal quarterly publication of the ACM Special Interest
Group on Computer Architecture (SIGARCH).  It contains approximately
400!!! references.

> What interests me most is work done on simple caches for multi-processors
> (so not the things that don't write through, and need funny memory
> boards that know their copy of a word is invalid, etc),
> and how they perform. The performance I'm most interested in is
> in keeping the bus free, not speeding up the processor.

Perhaps for a very immediate application it is best to stick to
write-thru caches for your multiprocessor, but you might look to
the IEEE P896 Futurebus for ways to build economical shared memory
multiprocessors with copy-back caches.  The Futurebus has explicit
support for caches called "three party transactions" that allow a
cache holding dirty data to dynamically disable the memory module
and respond in its place.  Memory modules are not burdened with special
requirements like valid bits.  The cache coherence specification,
P986.2, is now being written, and an informal description appeared
in the September 9 issue of Electronic Design.