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From: davet@oakhill.UUCP (Dave Trissel)
Newsgroups: net.micro.68k
Subject: Re: 68030 data cache vs. IO devices
Message-ID: <789@oakhill.UUCP>
Date: Fri, 10-Oct-86 02:35:56 EDT
Article-I.D.: oakhill.789
Posted: Fri Oct 10 02:35:56 1986
Date-Received: Sat, 11-Oct-86 19:39:28 EDT
References: <1007@zog.cs.cmu.edu>
Reply-To: davet@oakhill.UUCP (Dave Trissel)
Distribution: net
Organization: Motorola Inc. Austin, Tx
Lines: 29
Keywords: Apparent incompatibility

In article <1007@zog.cs.cmu.edu> tgl@zog.cs.cmu.edu (Tom Lane) writes:
>
>Problem #1: if the chip decides to cache the value read from an
>I/O device status register, subsequent reads will not produce the
>current contents of that register.

Just like the MC68851 Paged Memory Management Unit for the MC68020 the
MC68030 MMU descriptors support a cache inhibit status bit.  This forces
all bus cycles on pages so marked to bypass the on-chip caches.  All I/O
devices are normally attached to contiguous memory blocks so the only
requirement is to have the cache inhibit bit set for the descriptors
associated with these blocks.

>This problem also applies to shared variables in a multi-CPU, shared
>memory machine (which is supposedly a design target for Motorola ...
>remember TAS, CAS and them other funny instructions?)

Several solutions here.  First, the cache inhibit bit can be set for sharable
memory as described above.  Second, any external bus read request by the
processor can have the data returned with a signal indicating that it should
not be cached.  Of course, if you have an O.S. which arbitrarily makes all
memory sharable (this is rare) you can always disable the data cache, a rather
extreme thing to have to do.  We are at present examining ways to get around
this last solution.

All instructions which lock the external CPU (such as though you mentioned)
always by pass the on-chip data cache.

  -- Dave Trissel Motorola, Austin  {ihnp4,siesmo}!ut-sally!im4u!oakhill!davet