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From: tomj@oakhill.UUCP (Tom Johnson)
Newsgroups: net.micro.68k,net.micro.amiga,net.micro.atari16,net.micro.mac
Subject: Re: The Motorola 68030
Message-ID: <783@oakhill.UUCP>
Date: Tue, 30-Sep-86 10:44:24 EDT
Article-I.D.: oakhill.783
Posted: Tue Sep 30 10:44:24 1986
Date-Received: Wed, 1-Oct-86 06:19:45 EDT
References: <2270@gitpyr.UUCP> <1837@well.UUCP>
Reply-To: tomj@oakhill.UUCP (Tom Johnson)
Distribution: net
Organization: Motorola Inc. Austin, Tx
Lines: 22
Keywords: new motorola chips mmu fast
Xref: watmath net.micro.68k:1894 net.micro.amiga:5041 net.micro.atari16:2259 net.micro.mac:8050
Summary: 40 MB/s <> 25 ns memory

In article <1837@well.UUCP> swalton@well.UUCP (Stephen R. Walton) writes:
>
>>The bus data transfer rate of the 68030 is 40 Mbytes/sec.
>
>Think about this.  That's a memory access time of 25 nanoseconds, more than
>4 times as fast as the memory we use in our PC's, Macs, Amigas, and Apples.
>...
>Unless one of you hot-shot chip designers out there can put together a
>1 MB DRAM with 25 ns access which will sell for less than $100 apiece :->
>
>			Stephen Walton, speaking for myself

Try again, just because there is a 40MB/s bus transfer rate *does not* mean
that there is a 25 ns bus cycle!  If the processor transfers 4 bytes/xfer,
then the bus transfer rate will be 40 MB/s on a **100** ns bus cycle time.
If the transfer is 2 bytes/xfer then the bus cycle would be 50ns, etc.
Additionally, your assumption does not take into account capabilities such
as those on the 68030 to support new DRAM technology (page mode, static
column, nibble mode) which allows the transfer of 4 long words (16 bytes)
in as little as 5 clock cycles.

tom johnson            inhp4!ut-sally!oakhill!tomj