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From: olson@endor.harvard.edu (Eric Olson)
Newsgroups: net.micro.68k,net.micro.amiga,net.micro.atari16,net.micro.mac
Subject: Re: The Motorola 68030
Message-ID: <294@husc6.HARVARD.EDU>
Date: Wed, 1-Oct-86 12:53:13 EDT
Article-I.D.: husc6.294
Posted: Wed Oct  1 12:53:13 1986
Date-Received: Fri, 3-Oct-86 00:56:03 EDT
References: <2270@gitpyr.UUCP> <1837@well.UUCP> <783@oakhill.UUCP>
Sender: news@husc6.HARVARD.EDU
Reply-To: olson@endor.UUCP (Eric Olson)
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Organization: Aiken Computation Lab, Harvard University
Lines: 40
Keywords: new motorola chips mmu fast
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In article <783@oakhill.UUCP> tomj@oakhill.UUCP (Tom Johnson) writes:
>In article <1837@well.UUCP> swalton@well.UUCP (Stephen R. Walton) writes:
>>
>>>The bus data transfer rate of the 68030 is 40 Mbytes/sec.
>>
>>Think about this.  That's a memory access time of 25 nanoseconds, more than
>>4 times as fast as the memory we use in our PC's, Macs, Amigas, and Apples.
>>...
>>			Stephen Walton, speaking for myself

>
>Try again, just because there is a 40MB/s bus transfer rate *does not* mean
>that there is a 25 ns bus cycle!  If the processor transfers 4 bytes/xfer,
>then the bus transfer rate will be 40 MB/s on a **100** ns bus cycle time.
>...
>tom johnson            inhp4!ut-sally!oakhill!tomj

The 68020 (and presumably, the 030) has input lines asking the external
device (memory, peripheral, etc) how wide it is.  That way the processor
can ask for a long from a byte-wide device and do 4 reads after the device
says "but I'm only a little bitty byte wide".  But I would be frightened
away from an architecture where a true 32 bit processor has byte-wide main
memory.  Still, you build the machine with the fastest memory you can afford,
and if it ain't fast enough, use wait states.  Faster processor speed is still
significant, especially in a processor with an on-chip cache.  Remember:
memory halfs in cost and doubles in speed every n years (where n used to be
5, and seems to be approaching 1).  I realize there is a theoretical limit,
until we all wise up and start using transphasors (transistors that switch
laser light).  

This brings up an interesting point.  In the mid-70's, everyone started
making processors with MORE instructions that do MORE processing each.  This
was, in part, due to memory bandwidth limitations.  The new genre of RISC
machines is going exactly the other way:  processors with FEWER instructions,
each of which does LESS processing, because memory bandwidth has improved.
The RISC concept allows more specific manipulation of processing power (and
therefore requires more intelligent compilers, to take advantage of the
quantization of the processing unit).  When's the 78000 due out?

-Eric