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From: hansen@mips.UUCP (Craig Hansen)
Newsgroups: comp.arch,comp.lang.c
Subject: Re: sizeof(char)
Message-ID: <764@mips.UUCP>
Date: Wed, 12-Nov-86 15:22:57 EST
Article-I.D.: mips.764
Posted: Wed Nov 12 15:22:57 1986
Date-Received: Wed, 12-Nov-86 23:47:58 EST
References: <4617@brl-smoke.ARPA> <657@dg_rtp.UUCP>
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 24
Xref: mnetor comp.arch:15 comp.lang.c:25

> >>[...]  But I definitely want the
> >> next generation of desktop processors to support bit addressing.
> >
> >If you're going to convince Motorola, Intel, National Semiconductor, DEC,
> >MIPS, etc., etc.  to put bit-addressing into their next generation of chips,
> >[...]
> 

One reason to avoid bit-addressing is that it uses up three more bits of
addresses, pointers, offsets, etc.  Given a 32-bit word-size, which can be
reasonably expected to be the norm for some time, and that the IBM XA
conversion (as well as the 68010->68012/68030 conversion) indicates that
24-bit addressing isn't nearly enough, those three bits are remarkably
precious.

Of course, one can use word- or byte-address pointers with bit offsets,
but that isn't quite the same thing as a simple linear bit-address,
and is harder to manipulate.

-- 

Craig Hansen			|	 "Evahthun' tastes
MIPS Computer Systems		|	 bettah when it
...decwrl!mips!hansen		|	 sits on a RISC"