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From: kludge@gitpyr.gatech.EDU (Scott Dorsey)
Newsgroups: net.arch
Subject: Instruction Questions
Message-ID: <2469@gitpyr.gatech.EDU>
Date: Thu, 23-Oct-86 14:47:03 EDT
Article-I.D.: gitpyr.2469
Posted: Thu Oct 23 14:47:03 1986
Date-Received: Fri, 24-Oct-86 16:06:40 EDT
Reply-To: kludge@gitpyr.UUCP (Scott Dorsey)
Distribution: world
Organization: Georgia College Of Universal Knowledge
Lines: 15

Question: What is the effect on the efficiency of an instruction set due
to the exchange and conditiona return instructions.  Shades of Z-80dom,
huh?
By exchange I mean either a register-to-register exchange (very fast
with two internal busses), not a register-to-memory exchange (slow, unless
you have multiple data and address busses :-)), or core-to-core exchanges
(impossibly useless).

By conditional returns, I mean a return with the same format as the
conditional jump.  Return on carry would be great, return on parity
would not be so useful.

I have used these features on several machines and have become quite
depressed that they aren't found in may of the current generation of
microprocessors.