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From: kissell@garth.UUCP
Newsgroups: net.arch
Subject: Re: Floating point performance
Message-ID: <380@garth.UUCP>
Date: Thu, 23-Oct-86 04:05:17 EDT
Article-I.D.: garth.380
Posted: Thu Oct 23 04:05:17 1986
Date-Received: Sat, 25-Oct-86 05:44:51 EDT
References: <340@euroies.UUCP> <1989@videovax.UUCP> <722@mips.UUCP> <8184@sun.uucp> <725@mips.UUCP>
Reply-To: kissell@garth.UUCP (Kevin Kissell)
Organization: Fairchild APD -- Palo Alto, CA
Lines: 9

In article <725@mips.UUCP> mash@mips.UUCP (John Mashey) writes:
>                                                       Right now, at least
>in anything close to 2micron CMOS, if the FPU is part of the CPU chip, it
>just has to be heavily microcoded.

Oh?  What law of physics are we violating?  ;-)

Kevin D. Kissell
Fairchild Advanced Processor Division