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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: net.arch
Subject: Re: Floating point performance & Mr
Message-ID: <7256@utzoo.UUCP>
Date: Sat, 25-Oct-86 21:13:04 EDT
Article-I.D.: utzoo.7256
Posted: Sat Oct 25 21:13:04 1986
Date-Received: Sat, 25-Oct-86 21:13:04 EDT
References: <1198@hoptoad.uucp> <30200001@gorgo.UUCP>, <13508@amdcad.UUCP>
Organization: U of Toronto Zoology
Lines: 10

> ... the last time I checked, cycle time
> doesn't vary with addressing mode, even on the CISCiest of CISCs...

Varying cycle time is not uncommon in the PDP11 line, at least in the 11s
I've had cause to investigate in detail.  The microcode selects the cycle
time it wants on a cycle-by-cycle basis, presumably with the delays of
different processor sections in mind.
-- 
				Henry Spencer @ U of Toronto Zoology
				{allegra,ihnp4,decvax,pyramid}!utzoo!henry