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From: mash@mips.UUCP (John Mashey)
Newsgroups: net.arch
Subject: Re: Floating point performance & Mr. Mashey's Mythical Mhz
Message-ID: <747@mips.UUCP>
Date: Wed, 29-Oct-86 03:09:40 EST
Article-I.D.: mips.747
Posted: Wed Oct 29 03:09:40 1986
Date-Received: Fri, 31-Oct-86 01:46:27 EST
References: <340@euroies.UUCP> <1989@videovax.UUCP>
Reply-To: mash@mips.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 40

In article <21944@rochester.ARPA> crowl@rochtest.UUCP (Lawrence Crowl) writes:
>>>In article <727@mips.UUCP> mash@mips.UUCP (John Mashey) writes:
> ... MWhets/Mhz, etc, as way to factor out transient technology...
>
>Perhaps what we are missing is that for a given level of technology, a longer
>clock cycle allows us to have a larger depth of combinational circuitry.  That
>is, we can have each clock work through more gates.  So, a 4 MHz clock which
>governs propogation through a combinational circuit 4 gates deep will do
>roughly the same work as a 1 MHz clock governing propogation through a
>combinational circuit 16 gates deep.  Perhaps a better measure is the depth of
>gates required to implement a FLOP, (or an instruction, or a window, etc.).
Can you suggest some numbers for different machines? One of the reasons
I proposed a (simplsitic) measure is the absolute difficulty of finding
such thing out.
>
>
>BOLD UNSUPPORTED CLAIM: The "best" architecture is technology dependent.  The
>quality of an architecture is dependent on the technology used to implement it,
>and no architecture is "best" under more than a limited range of technologies.
>For instance, under technologies in which the bandwidth to memory is most
>limited, stack architectures (Burroughs, Lilith) will be "better".  Under 
>technologies where the ability to process instructions is most limited, the
>wide register to register architectures will be "better".

Much of this seems true.  We always claim that the real meaning of RISC in
VLSI RISC is "Response to Inherent Shifts in Computer technology", i.e
in hardware: fast, dense, cheap SRAMs; higher-pincount VLSI packages,
and in software: more use of high-level languages; portable OS's like UX/.
In the days of core memories, it is likley that the more aggressively
undense RISCs [i.e., those with only 32-bit instructions] would have
been bad ideas for anything but high-end machines.
Given: TTL, NMOS, CMOS, ECL, GaAs, for example, it would be interesting to
hear what people think who are / have implmented same machine over multiple
technologies [such as DEC VAXen, IBM 370s, HP SPectrums, all of which 
are supposed exist in at least 3 of the first 4 of the above; I think most
GaAs designs are RISCs, given smaller gate counts.]
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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