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From: campbell@sauron.UUCP (Mark Campbell)
Newsgroups: net.arch
Subject: I80386 Multiprocessing and External Caches
Message-ID: <749@sauron.UUCP>
Date: Thu, 30-Oct-86 19:11:49 EST
Article-I.D.: sauron.749
Posted: Thu Oct 30 19:11:49 1986
Date-Received: Mon, 3-Nov-86 23:05:56 EST
Distribution: net
Organization: NCR Corp., Advanced System Development, Columbia, SC
Lines: 18

Question #1:
Has anyone out there looked at the I80386 with respect to multiprocessing?
In particular, how would you handle the lack of a CIOUT-like signal (MC68030)
which would allow dynamic disabling of an external cache on accesses to
specified pages?  If two processes on two different processors had shared
memory between them, it would seem impossible to maintain data integrity
if both processors had local data caches.

Question #2:
Looking at the timing diagrams of the I80386, it would appear that if
NA were constantly asserted you'd get rid of the address valid delay
times (32ns at 20MHz) at the beginning of a cycle so that you'd have
a lot more time to handle your cache tag compare.  All it would cost would
be the latching of addresses from the processor.  Any comment and/or
correction?
-- 

Mark Campbell    Phone: (803)-791-6697     E-Mail: !ncsu!ncrcae!sauron!campbell