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From: john@frog.UUCP (John Woods, Software)
Newsgroups: net.micro.68k
Subject: Re: 68030 data cache vs. IO devices
Message-ID: <1089@frog.UUCP>
Date: Fri, 24-Oct-86 13:07:42 EST
Article-I.D.: frog.1089
Posted: Fri Oct 24 13:07:42 1986
Date-Received: Sun, 26-Oct-86 07:48:50 EST
References: <1007@zog.cs.cmu.edu> <7213@utzoo.UUCP>
Organization: Superfrog Heaven [ CRDS, Framingham MA ]
Lines: 25

> > ...  Is there
> > a mechanism for keeping certain (ranges of?) addresses from being
> > cached?  ...
> 
> The orthodox solution to the problem is to have a "don't cache" bit in
> the page table entries, and have the MMU and the cache collaborate so
> that pages with that bit on do not get cached.  Given that both the MMU
> and the cache are on-chip in the 030, that is probably what Motorola
> has done.  (I don't remember the PMMU specs well enough to know whether
> it has provisions for this...)
> -- 
> 				Henry Spencer @ U of Toronto Zoology
> 				{allegra,ihnp4,decvax,pyramid}!utzoo!henry
> 

The PMMU has a "don't even THINK of caching references through me" bit in
the PTEs (or whatever they are called).  For amusement's sake, there is also
a "don't cache this reference" pin coming into the chip; I suppose that a
system running with the PMMU disabled could use address decoders to recognize
"the IO page" and specifically disable caching for it.

--
John Woods, Charles River Data Systems, Framingham MA, (617) 626-1101
...!decvax!frog!john, ...!mit-eddie!jfw, jfw%mit-ccc@MIT-XX.ARPA

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