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Path: utzoo!mnetor!seismo!lll-crg!rutgers!clyde!ima!haddock!karl
From: karl@haddock.UUCP (Karl Heuer)
Newsgroups: comp.arch,comp.lang.c
Subject: Bit addressibility (was: sizeof(char))
Message-ID: <172@haddock.UUCP>
Date: Sat, 15-Nov-86 09:23:30 EST
Article-I.D.: haddock.172
Posted: Sat Nov 15 09:23:30 1986
Date-Received: Sun, 16-Nov-86 01:15:20 EST
References: <4617@brl-smoke.ARPA> <657@dg_rtp.UUCP>
Reply-To: karl@haddock.UUCP (Karl Heuer)
Organization: Interactive Systems, Boston
Lines: 23
Xref: mnetor comp.arch:23 comp.lang.c:51

In article <764@mips.UUCP> hansen@mips.UUCP (Craig Hansen) writes:
>> >>[...]  But I definitely want the
>> >> next generation of desktop processors to support bit addressing.
>> >
>> >If you're going to convince Motorola, Intel, National Semiconductor, DEC,
>> >MIPS, etc., etc.  to put bit-addressing into their next generation of chips,
>> >[...]
>
>One reason to avoid bit-addressing is that it uses up three more bits of
>addresses, pointers, offsets, etc.  Given a 32-bit word-size, which can be
>reasonably expected to be the norm for some time, and that the IBM XA
>conversion (as well as the 68010->68012/68030 conversion) indicates that
>24-bit addressing isn't nearly enough, those three bits are remarkably
>precious.

I suspect that in the not-too-distant future, 32-bit addressing will be "not
nearly enough".  If I were designing a new architecture, I'd give it 64-bit
pointers -- which ought to take a LONG time to overflow, so the machine
wouldn't be obsolete next year.  And even if I didn't plan to support bit-
addressing, I'd reserve the lowest three bits (Must-Be-Zero) so that the next
compatible generation would still have the option available.

Karl W. Z. Heuer (ima!haddock!karl or karl@haddock.isc.com), The Walking Lint