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From: roger@telesoft.UUCP (Roger Arnold @prodigal)
Newsgroups: comp.arch
Subject: Re: Connection Machine Argument
Message-ID: <367@telesoft.UUCP>
Date: Thu, 4-Dec-86 16:44:23 EST
Article-I.D.: telesoft.367
Posted: Thu Dec  4 16:44:23 1986
Date-Received: Fri, 5-Dec-86 10:45:59 EST
References: <745@husc6.UUCP>
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Organization: TeleSoft, SanDiego CA
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> The idea behind the Connection Machine architecture, of having an expensive
> hypercube interconnect with extremely simple 1-bit SIMD processors at the
> nodes, has bothered me quite a bit.  ...
> 
>      According to J. Ullman in COMPUTATIONAL ASPECTS OF  VLSI, chapter  
> 6,  the cost  of  a butterfly network in VLSI is O(n*n).  ...
> 
> ...  Since the size of the interconnect grows as n squared, it will be
> by  far  the  largest  component of a large system, and if we can
> replace each m simple processors by 1 complex processor, we will reduce
> the size of the  interconnect by m*m, and thus the size of the system...
> 
> 					Ehud Reiter
> 					reiter@harvard  (ARPA,UUCP)

I'm no authority on the connection machine, and perhaps I'm 
misinterpreting your argument, but is it not precisely the high cost
of the interconnect that dictates the use of 1-bit processors?  You
seem to be assuming that the size of the interconnect is independent
of the width of the data path, whereas it is probably close to linear.
It's most efficient to pump the bits serially through the network, and
if that's how they go over the network, that's how you want to process
them too.  As long as the processor cycle is matched to the network 
transmission speed, buffering for a wider processor just adds overhead, 
and buys nothing.

			      Roger Arnold
			      ..sdcsvax!telesoft!roger