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From: jnw@mcnc.UUCP (John White)
Newsgroups: comp.sys.intel
Subject: Re: Intialization of comp.sys.intel
Message-ID: <496@mcnc.mcnc.UUCP>
Date: Sun, 16-Nov-86 21:50:40 EST
Article-I.D.: mcnc.496
Posted: Sun Nov 16 21:50:40 1986
Date-Received: Tue, 18-Nov-86 09:27:13 EST
References: <400@intsc.UUCP>
Distribution: net
Organization: Microelectronics Center of NC; RTP, NC
Lines: 37
Summary: 486 ideas


> ... with an emphasis toward what enhancements should
> be done on the 486 and beyond (68020 and vax compatibility have already 
> been suggested).

     Well, I have some ideas about what might be nice on the 486. First
add I & D caches, with separate internal data paths to each (like the
68030 is supposed to have). Then add some sort of 1-transfer/cycle
memory access. The 68030 has a mode that allows 128bits from memory
to be multiplexed over the 32bit data bus at 1-transfer/cycle. This
is good for reading code, and most serious memory boards are at least
128 (+ parity&ECC) chips wide anyway.
     It might be nice to keep some kind of prefetch with the code, though.
If the 486 is executing a newly loaded block of 128bits, then it might
prefetch the next 128bits. If the 128bits currently being executed were
already in cache (and are being executed for the second or n'th time),
then this may be the bottom of a loop and so no prefetch should occur.
     A bus-error pin might also be useful to someone who wants to
have some external memory management, or who wants to have
software handling of memory ECC, or some other such thing.
The 386 has the internal capability to handle page-faults, but I
don't see any way of causing a page-fault type of interrupt externally.
I would think that this would be easy to add.
     Variable page sizes would also be nice. (2**n, of course).
By the time that the 486 is at the end of its useful life, there will be
systems using it that will have really massive amounts of memory. I expect
that some programs on these systems will do a more or less random access
to memory quite often. But the 386 has to load two TLB entries before
being able to access a random location in a big memory. If the pages
were large enough, however, the TLBs would be able to cache the whole
4Gbyte address space, and there would be no performance penalty for having
the memory management active.
     Also, a couple of pins could be added to the physical address bus.
With 16Kbyte pages, you could have a 16Gbyte physical memory (which could
hold several 4Gbyte logical address spaces).

Well, these ramblings should at least get some discussion going. -jnw@mcnc