Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!seismo!lll-crg!rutgers!clyde!cbatt!ihnp4!inuxc!pur-ee!uiucdcs!uiucuxc!clio!berger From: berger@clio.Uiuc.ARPA Newsgroups: comp.sys.m68k Subject: Re: Byte ordering, and pros/cons Message-ID: <16900001@clio> Date: Mon, 1-Dec-86 18:47:00 EST Article-I.D.: clio.16900001 Posted: Mon Dec 1 18:47:00 1986 Date-Received: Tue, 2-Dec-86 22:28:19 EST References: <1271@ihwpt.UUCP> Lines: 9 Nf-ID: #R:ihwpt.UUCP:1271:clio:16900001:000:434 Nf-From: clio.Uiuc.ARPA!berger Dec 1 17:47:00 1986 That's just not true. There IS some advantage to the Intel scheme when you're talking about chips with an 8 bit bus doing 16 bit address calculations. The low order byte is needed first, and is fetched from memory first - then the address counter is incremented. This is surely faster than incrementing the address counter, fetching, decrementing, fetching, and incrementing twice. This advantage is eliminated with a 16 bit bus.