Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!utgpu!water!watnot!watmath!clyde!rutgers!sri-unix!hplabs!decwrl!pyramid!oliveb!intelca!mipos3!cpocd2!howard
From: howard@cpocd2.UUCP
Newsgroups: comp.lsi
Subject: Re: Graphics Immage or Pattern recognition VLSI
Message-ID: <420@cpocd2.UUCP>
Date: Thu, 12-Feb-87 19:05:53 EST
Article-I.D.: cpocd2.420
Posted: Thu Feb 12 19:05:53 1987
Date-Received: Sun, 15-Feb-87 01:04:59 EST
References: <8702081207.AA26997@taurus>
Reply-To: howard@cpocd2.UUCP (Howard Landman)
Organization: Intel Corp. ASIC Services Organization, Chandler AZ
Lines: 27

In article <8702081207.AA26997@taurus> ami@taurus.BITNET (Amir Schorr) writes:
>I would like to know about Graphics or Immage or Parrern Recognition
>processors which are develope now in universies or VLSI companies;

One very interesting chip for image or pattern work is the GAPP (Geometric
Array Parallel Processor?) from NCR.  It consists of a 6 by 12 array of
bit-serial processors on a single chip.  Each processor has 128 bits of
memory (organized as 128 words of 1 bit each), a bit-serial ALU that can
sometimes do two or three operations in parallel (depending on which resources
the operations use), and communications channels to the four adjacent
processors on a square grid (or off chip if at the edge of the array).
The chips can be stacked in X and/or Y to get larger arrays.  There is
a development system available on IBM PC.

The chip (or array for chips) is an SIMD machine, since all processors
are attached to a global address and instruction bus.  For image procesing
you would typically shift in the image from one edge of the array, do the
computation, and shift out the result.

All in all, an interesting architecture.  But why 6 X 12?  Why not 8 X 8?

I have no connection with NCR except that I read their literature and work
for one of their competitors.
-- 

	Howard A. Landman
	...!intelca!mipos3!cpocd2!howard