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From: henry@utzoo.UUCP (Henry Spencer)
Newsgroups: comp.sys.m68k
Subject: Re: Comparing 68xxx's; really TLB misses
Message-ID: <7617@utzoo.UUCP>
Date: Tue, 3-Feb-87 16:24:13 EST
Article-I.D.: utzoo.7617
Posted: Tue Feb  3 16:24:13 1987
Date-Received: Tue, 3-Feb-87 16:24:13 EST
References: <809@imagen.UUCP> <561@elmgate.UUCP> <1090@msudoc.UUCP>
Organization: U of Toronto Zoology
Lines: 28

> 3) "Many people are shocked at the idea" : I hope this is passing: after
> all, the same technique is used on HP Spectrums [for sure], and
> on Celerity boxes [I think]...

Yes, the Celerity boxes use it.  Or at least, they did back when I read
the manual for one, when we were thinking of buying it.

There is some variation in how one handles the problem of making sure that
the TLB-miss handler does not get TLB misses.  I dimly recall that the MIPS
hardware makes it easy to reserve some TLB slots for the system.  On the
Celerity machines the kernel just has to be careful, as I recall.

If you want a really shocking idea, consider the latest notion from Cheriton
and his bunch at Stanford.  The CPU runs out of a cache, which is addressed
by virtual address (virtual address includes a process id to avoid flushing
on every context switch) and has very long cache lines (e.g. 128 bytes --
*bytes*, not *bits*).  There is also a small amount of local memory which
is accessible only in kernel mode.  Cache misses are handled entirely in
software, with a bit of hardware help for fast data moving.  Notice that
there is no MMU!  The virtual->real translation is needed only for handling
cache misses and can be done entirely by the software.  The only real issue
is whether software cache handling will be efficient enough.  Given a large
cache with a big line size, it just might work.  There are some other neat
tweaks to do cache-coherence handling for a multiprocessor system.  Very
new and very experimental, but a nice idea.
-- 
Legalize			Henry Spencer @ U of Toronto Zoology
freedom!			{allegra,ihnp4,decvax,pyramid}!utzoo!henry