Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!watmath!clyde!rutgers!sri-spam!mordor!lll-lcc!pyramid!prls!mips!mash
From: mash@mips.UUCP
Newsgroups: comp.sys.m68k
Subject: Re: move sr/move ccr: is bigger better?
Message-ID: <109@winchester.mips.UUCP>
Date: Tue, 3-Feb-87 02:36:41 EST
Article-I.D.: winchest.109
Posted: Tue Feb  3 02:36:41 1987
Date-Received: Wed, 4-Feb-87 03:38:41 EST
References: <809@imagen.UUCP> <561@elmgate.UUCP> <1090@msudoc.UUCP> <862@drivax.UUCP>
Reply-To: mash@winchester.UUCP (John Mashey)
Distribution: world
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 17
Keywords: logic? CCR Protection Memory Management

In article <862@drivax.UUCP> holloway@drivax.UUCP (Bruce Holloway) writes:
>
>From what I hear, the 68030 will have expanded caches, plus, possibly, data
>cacheing.

The 68030 is described as having both I-cache and D-cache on chip,
filled with burst-mode accesses, i.e., whenever they come out,
they will have [I think] 2 256-byte caches, each with 16 lines of 16 bytes each.
It will be interesting to see whether people turn the data-caching on or
not: depending on the benchmark and memory design, a tiny data cache
can actually make a system run slower, unlike the more usual speedup from
(even a small) I-cache. Just out of curiosity, does anybody out there
have any simulations for a 68K with this cache design?
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
UUCP: 	{decvax,ucbvax,ihnp4}!decwrl!mips!mash, DDD:  	408-720-1700, x253
USPS: 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086