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From: campbell@sauron.UUCP
Newsgroups: comp.sys.m68k
Subject: Re: move sr/move ccr: is bigger better?
Message-ID: <822@sauron.Columbia.NCR.COM>
Date: Wed, 4-Feb-87 13:24:38 EST
Article-I.D.: sauron.822
Posted: Wed Feb  4 13:24:38 1987
Date-Received: Sat, 7-Feb-87 11:59:20 EST
References: <809@imagen.UUCP> <561@elmgate.UUCP> <1090@msudoc.UUCP> <862@drivax.UUCP> <109@winchester.mips.UUCP>
Sender: news@sauron.Columbia.NCR.COM
Reply-To: campbell@sauron.UUCP (Mark Campbell)
Distribution: world
Organization: Advanced Systems Development, NCR Corp., Columbia, SC
Lines: 23
Keywords: logic? CCR Protection Memory Management

In article <109@winchester.mips.UUCP> mash@winchester.UUCP (John Mashey) writes:
> [...]
>It will be interesting to see whether people turn the data-caching on or
>not: depending on the benchmark and memory design, a tiny data cache
>can actually make a system run slower, unlike the more usual speedup from
>(even a small) I-cache. Just out of curiosity, does anybody out there
>have any simulations for a 68K with this cache design?

I believe that this holds only if the miss penalty for the small D-cache
causes one or more wait states to be induced when referencing the missed
location(1).  Since the best case access time of the MC68030 to external
memory is two wait states (synchronous mode) with or without the D-cache
I don't believe that the D-cache can cause a penalty in performance.

If anyone can think of cases in which this might not be true (i.e., cases
in which a small D-cache can cause a performance penalty under the stated
conditions) I'd appreciated your posting examples.  Thanks.

(1) This assumes a write-through cache and a relatively inexpensive
    cache flush operation (or that task switches are infrequent).
-- 
						Mark Campbell
						{}!ncsu!ncrcae!sauron!campbell