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From: howard@cpocd2.UUCP
Newsgroups: comp.arch
Subject: Re: subroutine frequency
Message-ID: <425@cpocd2.UUCP>
Date: Mon, 16-Feb-87 13:57:37 EST
Article-I.D.: cpocd2.425
Posted: Mon Feb 16 13:57:37 1987
Date-Received: Wed, 18-Feb-87 03:39:23 EST
References: <1881@homxc.UUCP> <898@moscom.UUCP> <476@mntgfx.MENTOR.COM> <651@mcgill-vision.UUCP>
Reply-To: howard@cpocd2.UUCP (Howard A. Landman)
Organization: Intel Corp. ASIC Services Organization, Chandler AZ
Lines: 16

In article <651@mcgill-vision.UUCP> mouse@mcgill-vision.UUCP (der Mouse) writes:
>In article <476@mntgfx.MENTOR.COM>, franka@mntgfx.MENTOR.COM (Frank A. Adrian) writes:
>> In article <898@moscom.UUCP> jgp@moscom.UUCP (Jim Prescott) writes:
>>>	a) save all registers
>>>	b) have the caller save only the registers it is using
>>>	c) have the callee save only the registers it will use

All this discussion, and no one's suggested using hardware to avoid saving
any registers at all (most of the time)!  This has been done in a few
machines; I'm most familiar with the RISC-I since I helped design the chip.
Isn't this a computer ARCHITECTURE group?  Did you know that HALF of the
memory traffic on a VAX-11/780 is data being saved/restored?
-- 

	Howard A. Landman
	...!intelca!mipos3!cpocd2!howard