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From: dupuy@amsterdam.columbia.edu.UUCP
Newsgroups: comp.arch
Subject: Using a DMA chip in strange ways
Message-ID: <4343@columbia.UUCP>
Date: Tue, 17-Feb-87 19:50:18 EST
Article-I.D.: columbia.4343
Posted: Tue Feb 17 19:50:18 1987
Date-Received: Thu, 19-Feb-87 06:18:05 EST
Sender: nobody@columbia.UUCP
Reply-To: dupuy@amsterdam.columbia.edu (Alexander Dupuy)
Distribution: world
Organization: Columbia University CS Department
Lines: 27


    While reading Tanenbaum's new OS book (the Minix book) a sort of half baked
idea came to me.  While sophisticated OS design strives to minimize the number
of memory to memory copies, there is some irreducible minimum in a system with
distinct user and kernel spaces.

    Since the DMA chip on your favorite disk/tape controller works by stealing
bus cycles when the CPU is busy with other things (like arithmetic), would
there be any advantage in having a DMA chip which would simply be used for
memory to memory copies (from user to kernel space, or from one user space to
another)?

    At some point the various DMA chips may start bumping into each other, and
it may not be worth the effort (in more complex bus access/arbitration logic)
to add this memory to memory DMA chip.  But given sufficient bus bandwidth, if
the CPU spends a significant amount of time without accessing the bus, there
could be a significant performance boost for current operating systems.

    So what do you hardware types think?  Is there anything to this idea?  Does
this sort of thing already exist, and I just don't know about it?  Or is there
some problem which I have missed?

@alex

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