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From: kds@mipos3.UUCP
Newsgroups: comp.arch
Subject: Re: Using a DMA chip in strange ways
Message-ID: <475@mipos3.UUCP>
Date: Wed, 18-Feb-87 16:43:56 EST
Article-I.D.: mipos3.475
Posted: Wed Feb 18 16:43:56 1987
Date-Received: Fri, 20-Feb-87 01:48:47 EST
References: <4343@columbia.UUCP>
Reply-To: kds@mipos3.UUCP (Ken Shoemaker ~)
Distribution: world
Organization: Intel, Santa Clara, CA
Lines: 29

like has been said before, most DMA chips can be set up to do this, but...
...whether what you are suggesting is effective depends on the system.  I
believe that the 680[12]0 and the [23]86 processors are capable of moving
data across the entire width of the data bus at the maximum bus bandwidth,
so to move your data around as quickly you'd have to have a 32-bit dma
chip around that can also run at the maximum processor bandwidth.  Also, the
setup time at the beginning of the transfer is probably going to be longer,
since it usually takes longer just to set one of these things up, and if
it is sitting on the other side of the memory management, you have to take
that into account.  Also, whether it is going to really be effective is
dependent on whether the processor can really do something useful while
DMA is going on, since if it cannot gain access to the bus during the transfer,
it will just be sitting there anyway if it needs to get something from memory.
Some DMA controllers have a "throttle" which limits their maximum bus 
utilization to take care of this so the processor can get in a transfer
edgewise to take care of problems like this.

And another novel use of DMA controller?  I believe the original IBM pc uses
a DMA controller to do DRAM refresh.
-- 
The above views are personal.

The primary reason innumeracy is so pernicious is the ease with which numbers
are invoked to bludgeon the innumerate into dumb acquiescence.
			- John Allen Paulos

Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, California
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