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From: bcase@amdcad.UUCP
Newsgroups: comp.arch
Subject: Re: 01/31/87 Dhrystone Results and Sour
Message-ID: <14932@amdcad.UUCP>
Date: Mon, 23-Feb-87 13:24:59 EST
Article-I.D.: amdcad.14932
Posted: Mon Feb 23 13:24:59 1987
Date-Received: Thu, 26-Feb-87 19:32:46 EST
References: <2348@homxb.UUCP> <28200008@ccvaxa>
Reply-To: bcase@amdcad.UUCP (Brian Case)
Organization: Advanced Micro Devices, Sunnyvale, California
Lines: 21

In article <28200008@ccvaxa> aglew@ccvaxa.UUCP writes:
>Unless registers are actually only bound at link time.
>NOPping out the register save instructions would be trivial,
>and not cost too much.
>I read a paper that seemed to imply that Cray was attempting something
>similar. Has anything more come of this?
>
>Andy "Krazy" Glew. Gould CSD-Urbana.    USEnet:  ihnp4!uiucdcs!ccvaxa!aglew
>1101 E. University, Urbana, IL 61801    ARPAnet: aglew@gswd-vms.arpa

Re:  Binding/allocating registers at link time.  See a *very* good paper
by Wall in the Summer SIGPLAN conference on Compiler Construction.  This
paper describes a method to get the performance benefit of a stack-cache
style register file (e.g. Berekely register windows) from a fixed set
of registers (e.g. almost anything else).  This work was done for the DEC
Titan RISC machine with excellent results (but hey, the machine has 64
registers).

    bcase
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