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From: eppstein@tom.columbia.edu.UUCP
Newsgroups: comp.arch
Subject: register window machine questions
Message-ID: <4376@columbia.UUCP>
Date: Tue, 24-Feb-87 13:54:01 EST
Article-I.D.: columbia.4376
Posted: Tue Feb 24 13:54:01 1987
Date-Received: Thu, 26-Feb-87 23:27:38 EST
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Organization: Columbia University CS Department
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Register window machines such as the Berkeley RISCs have been discussed
recently in this group.  I have some questions about these architectures:

(1) Has anyone tried making the window block size be just one register,
i.e. the window can have an arbitrary alignment in relation to memory?
I would expect this to be more efficient in terms of registers used (and
therefore also memory), but register access time might suffer.

(2) Do any architectures dribble out dirty registers near the bottom of
the set of on-chip registers in otherwise unused memory cycles, or
similarly dribble them in when they move back on-chip rather than
stopping everything else while bringing them back in?

(3) Are there machines with both dynamic (windowed) and static (normal)
registers?  For instance it might be useful for quick O.S. interrupts to
use only statics and not go to the trouble of setting up a register
window stack (which would involve lots of reads and writes moving the
old stack completely out to memory and then back again later).  Static
registers could also be useful for non-local variables.
-- 
David Eppstein, eppstein@cs.columbia.edu, Columbia U. Computer Science Dept.