Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!utgpu!water!watnot!watmath!clyde!rutgers!lll-lcc!styx!ames!ucbcad!ucbvax!decvax!decwrl!pyramid!oliveb!intelca!mipos3!cpocd2!howard
From: howard@cpocd2.UUCP
Newsgroups: comp.arch
Subject: Re: register window machine questions
Message-ID: <448@cpocd2.UUCP>
Date: Wed, 25-Feb-87 13:32:45 EST
Article-I.D.: cpocd2.448
Posted: Wed Feb 25 13:32:45 1987
Date-Received: Sat, 28-Feb-87 01:44:20 EST
References: <4376@columbia.UUCP>
Reply-To: howard@cpocd2.UUCP (Howard A. Landman)
Organization: Intel Corp. ASIC Services Organization, Chandler AZ
Lines: 63

In article <4376@columbia.UUCP> eppstein@tom.columbia.edu (David Eppstein) writes:
>Register window machines such as the Berkeley RISCs have been discussed
>recently in this group.  I have some questions about these architectures:
>
>(1) Has anyone tried making the window block size be just one register,
>i.e. the window can have an arbitrary alignment in relation to memory?
>I would expect this to be more efficient in terms of registers used (and
>therefore also memory), but register access time might suffer.

Decoding gets a lot more complicated, but this approach might have some merit
if the memory itself was expensive relative to the decoding (probably not the
case in any MOS technology).  The maximum number of useful windows is about
6 or 7 anyway, for the UNIX programs examined by the Berkeley group.  Beyond
that the increased access time costs more than the extra windows save.  Of
course, with finer granularity, the access time would grow more slowly ...

>(2) Do any architectures dribble out dirty registers near the bottom of
>the set of on-chip registers in otherwise unused memory cycles, or
>similarly dribble them in when they move back on-chip rather than
>stopping everything else while bringing them back in?

The Berkeley RISC machines don't have any unused memory cycles.  So for them,
the answer is no.  This exact matching of processor memory requirement to
available memory bandwidth is a subtle, powerful, and not-often-appreciated
feature of those architectures.

>(3) Are there machines with both dynamic (windowed) and static (normal)
>registers?

Even in the Berkeley RISCs, 10 or so of the 32 registers are "global",
meaning they are the same in all windows.  So, yes.

>For instance it might be useful for quick O.S. interrupts to
>use only statics and not go to the trouble of setting up a register
>window stack (which would involve lots of reads and writes moving the
>old stack completely out to memory and then back again later).

This is a severely muddled question.  Mu!  Register windows IN HARDWARE,
which is what we're discussing, require almost NO setup time.  So I don't
understand what "trouble" and "reads" and "writes" you're talking about.
If you are talking about context switches, then yes there is an increased
overhead since (depending on how you implement it) multiple windows of
registers may need to be saved.  But context switches occur about two
orders of magnitude less frequently (in UNIX) than calls/returns, and so
this has no significant performance impact.  As far as "quick O.S. interrupts"
are concerned, these only need one set of registers, and so can be treated
pretty much just like a procedure call (being careful not to use the
overlapped registers).  No context switch is necessary in most cases.
Again, interrupts occur far less frequently than calls/returns, and so
even if it wasn't easy to handle them efficiently, the performance effect
would be small.  The only exception might be extremely high speed real-time
applications.

>Static registers could also be useful for non-local variables.

That's what they get used for, all right.  It turns out that in C
virtually all arrays are global, for example, and if you're looping
through all the elements of one it's nice to keep the address in a
register.
-- 

	Howard A. Landman
	...!intelca!mipos3!cpocd2!howard