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Path: utzoo!utgpu!tmsoft!mason
From: mason@tmsoft.UUCP
Newsgroups: comp.arch
Subject: Re: register window machine questions
Message-ID: <115@tmsoft.UUCP>
Date: Fri, 27-Feb-87 19:34:25 EST
Article-I.D.: tmsoft.115
Posted: Fri Feb 27 19:34:25 1987
Date-Received: Sat, 28-Feb-87 08:12:59 EST
References: <4376@columbia.UUCP> <7284@boring.mcvax.cwi.nl>
Reply-To: mason@tmsoft.UUCP (Dave Mason)
Organization: TM Software Associates, Toronto
Lines: 21

In article <7284@boring.mcvax.cwi.nl> jack@boring.UUCP (Jack Jansen) writes:
>What I have in mind is a stackish machine, with an intelligent
>stack cache that will delay writes around the stack pointer
>(since there's a very good chance that they will never have
>to be written at all).

I have thought a fair amount about this.  The problem for really high
performance is that: as all the activity takes place around the stack pointer
it is difficult to get much pipelining in progress.  This means the cache
must be very fancy if you want to do Cray class machines, although RISC class
seems pretty easy.  I have toyed with this direction for a Ph.D. thesis.

>One of the advantages of this seems to be that compilers become
>simpler (no special cases for routines that run out of registers),

(But then all that fancy compiler technique the RISC people cite would be
a waste :-)
(But the compiler induced bug rate would certainly go down.)
-- 
	../Dave Mason,	TM Software Associates	(Compilers & System Consulting)
	..!{utzoo seismo!mnetor utcsri utgpu lsuc}!tmsoft!mason