Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watnot!watmath!clyde!rutgers!lll-lcc!ames!pioneer!lamaster From: lamaster@pioneer.UUCP Newsgroups: comp.arch Subject: Re: register saving on context switch Message-ID: <420@ames.UUCP> Date: Fri, 27-Feb-87 16:53:22 EST Article-I.D.: ames.420 Posted: Fri Feb 27 16:53:22 1987 Date-Received: Sun, 1-Mar-87 11:33:34 EST References: <4376@columbia.UUCP> <448@cpocd2.UUCP> <5763@amdahl.UUCP> Sender: usenet@ames.UUCP Reply-To: lamaster@pioneer.UUCP (Hugh LaMaster) Organization: NASA Ames Research Center, Moffett Field, Calif. Lines: 58 In article <5763@amdahl.UUCP> chuck@amdahl.UUCP (Charles Simmons) writes: >In article <448@cpocd2.UUCP> howard@cpocd2.UUCP (Howard A. Landman) writes: >>In article <4376@columbia.UUCP> eppstein@tom.columbia.edu (David Eppstein) writes: >>>[David implies that an interrupt requires a complete context switch >>>of writing all active windows to memory and reloading them after >>>handling the interrupt] >> >>[Howard points out that for an interrupt, the operating system code >>that handles the interrupt can promise not to trash active windows, >>and continue to use the existing stack. He also points out that >>context switches between user processes occur relatively infrequently >>and thus the overhead of writing out all active windows and reading in >>new windows on a context switch is not important.] > >I agree with this, so I'm going to change the subject slightly. Lately >I've been thinking about operating systems which would perform a complete >context switch on every interrupt. In particular, code for handling >interrupts would run in a restricted environment (ie user mode) where >their ability to accidentally trash other interrupt handlers, the operating >system, and device drivers would be minimized. > >My biggest problem with this concept is that context switching, even >on a machine with "only" 16 registers is extremely expensive. >I'd be interested in hearing about architechtures that minimize the >expense of a context switch. > Actually, if you have a fast, pipelined memory interface, it is not so expensive after all to save the complete context automatically. CDC and Cray have been doing various forms of this for many years. On the CDC 6000/7000 and Cyber 70 and 170 machines this is known as "exchange jump". The Cyber 205 actually swaps 256 registers in less than 200 CPU cycles (not to be confused with the longer memory cycles). It can do this because of the way the memory interface is structured. It may look "expensive", but simplifies register management so much that it is actually cheap. On the Cray-1 type machines, this automatic exchange jump feature includes only the small register sets, not the vector registers, because of the expense of saving 8 vector registers. So, the complexity of having to have operating system kernel code become aware of the state of vector registers and who they belong to is reintroduced. Anyway, automatic context saving is not pie in the sky. It works well and probably provides a net performance/price improvement on machines which are going to have a fast, pipelined memory interface anyway; many machines intended for engineering/ scientific/floating point intensive use DO, and more SHOULD. Hugh LaMaster, m/s 233-9, UUCP {seismo,topaz,lll-crg}!ames!pioneer!lamaster NASA Ames Research Center ARPA lamaster@ames-pioneer.arpa Moffett Field, CA 94035 ARPA lamaster@pioneer.arc.nasa.gov Phone: (415)694-6117 ARPA lamaster@ames.arc.nasa.gov "In order to promise genuine progress, the acronym RISC should stand for REGULAR (not reduced) instruction set computer." - Wirth ("Any opinions expressed herein are solely the responsibility of the author and do not represent the opinions of NASA or the U.S. Government")