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Path: utzoo!utcsri!greg
From: greg@utcsri.UUCP (Gregory Smith)
Newsgroups: comp.arch
Subject: Re: Using a DMA chip in strange ways
Message-ID: <4291@utcsri.UUCP>
Date: Wed, 4-Mar-87 08:57:59 EST
Article-I.D.: utcsri.4291
Posted: Wed Mar  4 08:57:59 1987
Date-Received: Wed, 4-Mar-87 19:28:30 EST
References: <4343@columbia.UUCP> <1257@uvacs.CS.VIRGINIA.EDU>
Reply-To: greg@utcsri.UUCP (Gregory Smith)
Organization: CSRI, University of Toronto
Lines: 31
Summary: 

Somebody writes:
>     Since the DMA chip on your favorite disk/tape controller works by stealing
> bus cycles when the CPU is busy with other things (like arithmetic), would
> there be any advantage in having a DMA chip which would simply be used for
> memory to memory copies (from user to kernel space, or from one user space to
> another)?

The Z80 DMA chip does this. It can copy from a moving memory address to
a moving memory address, or from a moving memory address to a constant
i/o address, or the reverse of the latter.

Actually, in most configurations, the DMA chip steals the bus whether
the CPU wants it or not - you still win since a DMA copy operation can
be done with two memory cycles per byte, and most CPU's don't allow
this.

The Z80 chip was the first DMA chip I ran into, and I was surprised to
find out that others were not like that (most others generate moving
memory addresses and control signals, and the I/O device must be wired
to place the data on the bus (or read it) during the memory cycle). With
the Z80 setup, the DMA chip addresses the I/O device, so if this device
is always ready, it needs no special hardware and doesn't 'know' it is
being addressed by the DMA chip rather than the CPU. If it is not always
ready, there is a control signal to throttle the DMA. The disadvantage
is that I/O transfers require two memory cycles per byte, whereas only
one is required in the usual setup.

-- 
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Greg Smith     University of Toronto      UUCP: ..utzoo!utcsri!greg
Have vAX, will hack...