Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!utgpu!water!watnot!watmath!clyde!cbatt!ihnp4!ptsfa!lll-lcc!styx!ames!ucla-cs!marc
From: marc@ucla-cs.UUCP
Newsgroups: comp.arch
Subject: Re: Will caches ever become obsolete?
Message-ID: <4765@shemp.ucla-cs.UCLA.EDU>
Date: Mon, 2-Mar-87 20:48:27 EST
Article-I.D.: shemp.4765
Posted: Mon Mar  2 20:48:27 1987
Date-Received: Wed, 4-Mar-87 20:33:31 EST
References: <3182@wateng.UUCP>
Sender: root@ucla-cs.UCLA.EDU
Reply-To: marc@CS.UCLA.EDU (Marc Tremblay)
Distribution: comp
Organization: UCLA Computer Science Department
Lines: 54
Keywords: cache, coherence problems

In article <3182@wateng.UUCP> hmthaker@wateng.UUCP (Hemi M. Thaker) writes:
>
>     My question is, then, with the current improvements in
>memory chips (ie. faster access, and greater densities), does
>anyone forsee a time in the distant future (> 3 or 4 years)
>that the speed of say, a 1Mb chip will be comparable to that
>of say a 1Kb ECL chip used in current caches?
>
>     In other words, will all the research being conducted
>for the cache coherency problems be a waste?  


	The question could also be stated as follow: "Will there 
still be some memory hierarchy mechanism in future computers"?
Indeed one could say that the availability of very dense and very
fast memory chips will eliminate secondary memory in the same way that
these chips will eliminate the the use of caches between the processor
and the main memory. Or will it...

	I don't think so. First of all there is always a price to pay
when the size of memory using VLSI chips is increased (regardless of the
technology used). A register file of 16 registers introduces less
delay than one of 32, right? (because of longer data buses and/or 
longer select lines. In the same way the access to the cache
will always be faster than one to main memory because its size is 
supposedly smaller, (in the case of direct mapping for example).

	Also if a 1Mb chip (I supposed that the author meant in CMOS)
becomes as fast as an ECL chip, it also means that the processor will
faster too, most likely using the same technology.

	One could argue that in the future the time of a Read/Write for
VLSI chips will be so short that it will not be a limiting factor 
anymore. For example in a pipeline processor the time allowed for 
the processor to read/write its operands could be so long (some 
picoseconds!) that there would be no need for caches.  Well in 
this case, the choice of the period of a subcycle should probably
be decreased to match the access time to the registers (memory) 
and the "execute" part in the processor should be furthermore pipelined.

	We will see VLSI memory chips replace secondary memory though,
only because its cost-performance ratio will be better than disc storage.
But once again the hierarchy will remain the same.

	In order to reduce the dependency between the size of a register
file and the delay of a Read (a larger register file introduces longer
delays), we designed (at UCLA) a register file with variable size windows which
does not increase the delays very much even if one doubles the size of 
the register file. For more information you can send me e-mail, or look
in the proceedings of HICSS-87.

					Marc Tremblay
					Computer Science Department
					UCLA