Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watnot!watmath!clyde!cbatt!ihnp4!ptsfa!lll-lcc!styx!mordor!sri-spam!ames!think!husc6!endor!reiter From: reiter@endor.UUCP Newsgroups: comp.arch Subject: Re: Will caches ever become obsolete? Message-ID: <1341@husc6.UUCP> Date: Wed, 4-Mar-87 11:31:49 EST Article-I.D.: husc6.1341 Posted: Wed Mar 4 11:31:49 1987 Date-Received: Fri, 6-Mar-87 06:04:55 EST References: <3182@wateng.UUCP> Sender: news@husc6.UUCP Reply-To: reiter@harvard.UUCP (Ehud Reiter) Distribution: comp Organization: Aiken Computation Lab Harvard, Cambridge, MA Lines: 22 Keywords: cache, coherence problems In article <3182@wateng.UUCP> hmthaker@wateng.UUCP (Hemi M. Thaker) writes: >that the speed of say, a 1Mb chip will be comparable to that >of say a 1Kb ECL chip used in current caches? > In other words, will all the research being conducted >for the cache coherency problems be a waste? Even if processor and memory chips are made with the same technology, the processor can access on-chip memory much faster than off-chip memory. So, even if CMOS is as fast as ECL, we still may want to make a cache of our processor's on-chip memory. Also, main memory is typically shared accessed by a bus with several masters (DMA I/O devices as well as CPU, perhaps several CPU's in a shared-memory multiprocessor), so somewhat complex (and slow) bus protocols may be required, and memory bandwidth must be shared. Processors may still benefit from a private unshared cache memory, even if the cache's memory chips are no faster than main memory's memory chips. I think caches will be around for quite a while! Ehud Reiter reiter@harvard (ARPA,BITNET,UUCP)