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From: ron@brl-sem.UUCP
Newsgroups: comp.arch
Subject: Re: register saving on context switch
Message-ID: <670@brl-sem.ARPA>
Date: Wed, 4-Mar-87 13:07:22 EST
Article-I.D.: brl-sem.670
Posted: Wed Mar  4 13:07:22 1987
Date-Received: Fri, 6-Mar-87 20:38:09 EST
References: <4376@columbia.UUCP> <448@cpocd2.UUCP> <5763@amdahl.UUCP> <542@houxv.UUCP>
Organization: Electronic Brain Research Lab
Lines: 11

In article <542@houxv.UUCP>, rdt@houxv.UUCP (R.TRAUBEN) writes:
 >  	Could anyone share with us how the CPU hardware and operating
 > 	system coordinate their response to a faulted copyback midway
 > 	thru an exchange jump?
 > 
 > 	Consider 2 cases of fault:  fault due to a
 > 	page not present (stack overflow) and fault due to a memory
 > 	parity error. 

Easy, first, the machines don't page.
Second, use better error correction, parity is for farmers.