Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watnot!watmath!clyde!cbatt!ihnp4!ptsfa!lll-lcc!pyramid!prls!mips!mash From: mash@mips.UUCP Newsgroups: comp.arch Subject: Re: register window machine questions Message-ID: <14@winchester.mips.UUCP> Date: Thu, 5-Mar-87 04:57:00 EST Article-I.D.: winchest.14 Posted: Thu Mar 5 04:57:00 1987 Date-Received: Sat, 7-Mar-87 02:22:02 EST References: <4376@columbia.UUCP> <448@cpocd2.UUCP> <495@apple.UUCP> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 21 In article <495@apple.UUCP> baum@apple.UUCP (Allen Baum) writes: >Ditzel et. al. have finally published details of the CRISP processor, >which is a chip implements a stack cache with 32 registers.... >.... They claim exceptional high hit >ratios on the stack cache, and performance of about 9x a VAX780 >running at 16Mhz (for some number of benchmarks including PCC-- >smaller benchmarks show 30x!). There are a number of other >architectural innovations, most importantly a zero cycle branch. >There are papers in both this weeks Compcon and ISSCC proceedings. Unfortunately, I wasn't able to catch either COMPCON, or Dave's later CRISP talk at Stanford, but I do believe that was X a 750, not a 780 [BTL-Research usually compares that way since they have 750s!]. From reports of the Stanford talk, I also heard (maybe somebody else can confirm): 13X (750) Dhrystone (11,000? hard to know what their 750s do?) 20X wc 30X Ackerman's function -- -john mashey DISCLAIMER: UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash, DDD: 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086