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From: ian@loral.UUCP
Newsgroups: comp.arch
Subject: Re: register saving on context switch
Message-ID: <1386@loral.UUCP>
Date: Wed, 4-Mar-87 16:09:51 EST
Article-I.D.: loral.1386
Posted: Wed Mar  4 16:09:51 1987
Date-Received: Sat, 7-Mar-87 04:30:06 EST
References: <4376@columbia.UUCP> <448@cpocd2.UUCP> <5763@amdahl.UUCP> <542@houxv.UUCP> <1430@navajo.STANFORD.EDU>
Reply-To: ian@loral.UUCP (Ian Kaplan)
Organization: Loral Instrumentation, San Diego
Lines: 45

In article <1430@navajo.STANFORD.EDU> billw@navajo.STANFORD.EDU (William E. Westfield) writes:
>
>So has anyone done research to see if it might be worthwhile to
>implement a machine with multiple sets of registers (say 16 sets
>of 64 registers, with register windows)?  This would cut down on
>the overhead of conext switching a lot assuming that not too many
>processes were "active" at once.  It would probably add a lot to
>the complexity of the system though...
>
>BillW


  The Xerox Dorado has multiple register sets and as a result has
  very fast context switch.  For information on the Dorado see

    "The Dorado: A High-Performance Personal Computer.  Three Papers"
    Xerox CSL-81-1 January 1981, Palo Alto Research Center
    3333 Coyote Hill Rd., Palo Alto, CA 94304

  These papers are well worth reading.  To quote from the first paper
  "A Processor for a High-Performance Personal Computer" by Butler W.
  Lampson and Kenneth A. Pier, page 7

    5.3 Task Specific State

    In order to allow the immediate task switching described above, the
    processor must be able to save and restore state within one microcycle.
    This is accomplished by keeping the vital state information throughout
    the processor not in a single rank of registers but in task specific
    registers.  These are actually implemented with high speed memory that
    is addressed by a task number.  Examples of task specific registera are
    the microcode program counter, the branch condition register, the
    microcode subroutine link register, the memory data register, and a
    temporary storage register for each task.  The number of the task whcih
    will execute in the next microcycle is broadcast throughout the
    processor and used to address the task specific registers.  Thus, data
    can be fetched from high speed task specific memories and be available
    for use in the next cycle.

		     Ian Kaplan
		     Loral Dataflow Group
		     Loral Instrumentation
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