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From: coln@hpl-opus.UUCP
Newsgroups: comp.os.cpm
Subject: Re: Fact sheet or info in the 8251 USART
Message-ID: <1550001@hpl-opus.HP.COM>
Date: Tue, 24-Feb-87 14:06:10 EST
Article-I.D.: hpl-opus.1550001
Posted: Tue Feb 24 14:06:10 1987
Date-Received: Fri, 27-Feb-87 07:12:06 EST
References: <1260@beta.UUCP>
Organization: HP Labs, Instrument Tech. Dept.
Lines: 48

To program the 8251:

The chip is programmed by writing a sequence of control words (bytes!) to the
control register.

1)  All programming goes to the same chip "address", so first you must insure 
    that the chip is in a known state.  One way to do this is a hardware
    reset, another is to write three "all zero" dummy bytes to the chip, and
    then a command instruction with the internal reset bit "one".  (This covers
    the case where the first two may be interpreted as "sync" characters.)

2)  Write a "mode" instruction to the control register:

	Assuming that you will use the chip in asynchronous mode:

	b7,b6 : stop bits : 00 invalid, 01 -> 1bit, 10 -> 1.5bits, 11 -> 2bits
	b5    : 0 -> odd parity, 1 -> even parity  (only if parity enabled)
	b4    : 0 -> parity disabled, 1 -> parity enabled
	b3,b2 : character size : 00 -> 5bit, 01 -> 6bit, 10 -> 7bit, 11 -> 8bit
	b1,b0 : clock factor : 00 -> sync mode, 01 -> 1x, 10 -> 16x, 11 -> 64x

3)  Write no "sync" characters, since I am assuming asynchronous operation.

4)  Write a "command" instruction to the control register:

	b7 : 1 -> enter "hunt" mode (only for sync operation, no effect here)
	b6 : 1 -> internal reset, next write will be "mode" instruction
	b5 : 1 -> request-to-send output will go active (note active low)
	b4 : 1 -> reset error flags: parity, overrun, framing
	b3 : 1 -> send "break" character (force transmitted data to 0)
	b2 : 1 -> receive enable
	b1 : 1 -> data-terminal-ready output will go active (note active low)
	b0 : 1 -> transmit enable

5)  now the chip should be working...

Therefore, for your requested parameters of 7 data, parity, and 1 stop:

	00000000 (sync) dummy sync if reading sync characters
	00000000 (sync) second dummy sync
	00000000 (command) dummy command
	01000000 (command) internal reset
	01111010 (mode) even parity or 01011010 odd parity, both 16x clock
	00100111 (command) example with both RTS and DTR active

I hope I got this right, and that it is the information you need.

		Mike Coln