Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watnot!watmath!clyde!cbatt!ihnp4!houxm!mtuxo!mtune!ariel!caelum!io!jlw From: jlw@io.UUCP Newsgroups: comp.sys.m6809 Subject: Re: 512K and wimpy GIME chips Message-ID: <220@io.UUCP> Date: Wed, 18-Feb-87 16:37:12 EST Article-I.D.: io.220 Posted: Wed Feb 18 16:37:12 1987 Date-Received: Fri, 20-Feb-87 00:53:05 EST References: <1404@ihwpt.UUCP> Organization: AT&T IS Labs, Middletown NJ USA Lines: 15 One problem you might be running into is a peculiarity of the WECo 256K DRAM. 256K DRAMs have A0-A8 strobed twice with CAS and RAS respectively. Since the architecture of a 256K chip is really a 4x64K only A0-A7 are active for refreshing. If your board design tri-states A8 of a WECo. 256K DRAM during refresh, your data will die. The real problem is that this is very hard to determine with standard memory check programs since they access the memory often enough to keep it refreshed. Then when you try to run real code.....boom...Panic Trap. Joe Wood io!jlw