Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!mnetor!seismo!ll-xn!ames!oliveb!sun!gravity!klein
From: klein%gravity@Sun.COM (Mike Klein)
Newsgroups: comp.arch
Subject: Re: Am29000 and MIPS
Message-ID: <15243@sun.uucp>
Date: Wed, 18-Mar-87 12:00:10 EST
Article-I.D.: sun.15243
Posted: Wed Mar 18 12:00:10 1987
Date-Received: Fri, 20-Mar-87 01:33:13 EST
References: <15192@amdcad.UUCP> <1423@husc6.UUCP>
Sender: news@sun.uucp
Reply-To: klein@sun.UUCP (Mike Klein)
Organization: Sun Microsystems, Mountain View, CA
Lines: 23
Keywords: RISC MIPS

In article <1423@husc6.UUCP> reiter@harvard.UUCP (Ehud Reiter) writes:
>In article <15192@amdcad.UUCP> bcase@amdcad.UUCP (Brian Case) writes:
>>The Am29000 ...  25 MHz clock (40 ns cycle time) ...
>>25 MIPS max., 17 MIPS sustained running big programs
>
>I don't mean to criticize the Am29000, which I'm sure is a fine machine.  But
>in the interest of taking whatever feeble measures are possible to reduce the
>confusion level in this area, I wish people would stick to definition (a)
>of "MIPS", unless they explicitly say they're using definition (b).

In this case, the meaning of Brian Case's MIPS should be pretty obvious.
A 40 nS cycle means 25 peak MIPS, for the case where the Am29000 is executing
a loop of NOPs out of its on-board I cache (as one example).  Elsewhere, I saw
it mentioned that the average (simulated) cycles per instruction on this
machine is about 1.5 on large C programs; dividing 25 MIPS by 1.5 gives you
16.67 MIPS.  Neither number is a comparison against a VAX/780.

I don't see any numbers on the performance impacts of things like cache misses,
interrupts, and the processor running an operating system.
--
	Mike Klein		klein@sun.{arpa,com}
	Sun Microsystems, Inc.	{ucbvax,hplabs,ihnp4,seismo}!sun!klein
	Mountain View, CA