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From: lawrenc@nvanbc.UUCP (Lawrence Harris)
Newsgroups: comp.arch
Subject: Re: 64 Vs 32 (386 addressing)
Message-ID: <390@nvanbc.UUCP>
Date: Thu, 19-Mar-87 04:27:59 EST
Article-I.D.: nvanbc.390
Posted: Thu Mar 19 04:27:59 1987
Date-Received: Sat, 21-Mar-87 10:17:06 EST
References: <3810013@nucsrl.UUCP> <28200016@ccvaxa> <4372@utcsri.UUCP>
Reply-To: lawrenc@nvanbc.UUCP (Lawrence Harris)
Organization: L.H. Computing
Lines: 26

In article <4372@utcsri.UUCP> greg@utcsri.UUCP (Gregory Smith) writes:
>In article <28200016@ccvaxa> aglew@ccvaxa.UUCP writes:
>
>An inference: from the description in the article, I have to conclude
>that the 386 has its own instruction set ( the 286 opcode space is too
>full, and does not contain the kind of instructions that you would want
>in a 32-bit machine, or the addressing modes described in the article).
>Thus the 386 has two instruction modes (386/286 opcodes). I imagine the
>286 instructions are available with different encoding (and probably
>different addressing) within the 386 set. Maybe they'll make one that
>runs 6502 code too so we can make Apple-compatible PC's.
>
No, the 386 uses the same binary instruction encoding as the 286.  It
adds a new mode byte for extended addressing modes, and a bit in the
segment descriptor for a code segment which tells the processor whether
the code in this segment is to be 16 or 32 bit integer.  There is also
a prefix byte to switch an individual instruction to the opposite size.

I am told that XENIX V/286 runs on the Compaq 386 right out of the box
so the cpu's must be very compatable at the binary level.

Also there is another bit which says whether the segment size is in bytes
or increments of (I think) 16 bytes, this is how you can have segments up
to 1Mb now.

I believe there was a recent article in byte magazine on the 386.