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From: tim@amdcad.UUCP
Newsgroups: comp.arch
Subject: Re: Am29000 & register windows
Message-ID: <15251@amdcad.UUCP>
Date: Sat, 21-Mar-87 12:47:53 EST
Article-I.D.: amdcad.15251
Posted: Sat Mar 21 12:47:53 1987
Date-Received: Sun, 22-Mar-87 21:40:26 EST
References: <118@neptune.AMD.COM> <722@instable.UUCP>
Distribution: world
Organization: AMDCAD, Sunnyvale, CA
Lines: 20
Summary: stack cache vs register banks

In article <722@instable.UUCP>, amos@instable.UUCP (Amos Shapir) writes:
> I have just read the piece in Elctronics magazine; nice hype - they even
> have a picture of the (yet non-existent) chip. Hype aside, it looks like
> a compiler writer's dream - 192 registers! But then came the part about
> the 700ns context-switch time - that cannot include saving & restoring
> all registers, can it? If it doesn't, who amd how takes care of keeping
> track of who uses what and when? (I hope I'm making myself clear :-))

The context switch time quoted was for the register bank model, where eight
separate contexts can be stored on-chip.  Each context has 16 general
registers (which uses the local register set) and 8 registers used to save
state information while the process is not running (processor status,
Q register, etc.), stored in global registers.  A context switch simply
consists of saving the state information of the current process, restoring
the state information for the next process, and changing the internal stack
pointer to point to the new general register bank.

	-- Tim Olson
	Advanced Micro Devices
	(tim@amdcad)