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From: bcase@amdcad.UUCP
Newsgroups: comp.arch
Subject: Re: String Processing Instruction
Message-ID: <15326@amdcad.UUCP>
Date: Mon, 30-Mar-87 17:48:30 EST
Article-I.D.: amdcad.15326
Posted: Mon Mar 30 17:48:30 1987
Date-Received: Thu, 2-Apr-87 00:52:38 EST
References: <15292@amdcad.UUCP> <978@ames.UUCP> <909@spar.SPAR.SLB.COM>
Reply-To: bcase@amdcad.UUCP (Brian Case)
Distribution: na
Organization: Advanced Micro Devices, Sunnyvale, California
Lines: 21

In article <15325@amdcad.UUCP> bcase@amdcad.UUCP (Brian Case) writes:
>Like oops:  the fact that we use the 29000 as a word-addressed machine in
>our simulations is so familiar to me that I forgot to mention it as an
>assumption.  It is important to note that the 29000 can be used as either
>a word-addressed or as a byte-addressed machine:  there are 3 "user bits"
>in the load/store control fields that simply drive some pins on the chip.
>Thus, they can be used to encode things like load/store byte/halfword/word
>if a system implementor so chooses.  However, we think it is stupid because
>such things slow down memory systems and thus the entire system.  But if
>you really want to....

Jeeze louise, I forgot to mention that the Am29000 always drives the
entire byte address on the pins.  It's just that the preferred memory
system implementation ignores the lower two bits and always returns a full
word.  In this case, the byte-extract and byte-insert instructions are
used once the word gets on chip.  (For RISC historians:  The paper
"Hardware/Software Tradeoffs for Increased Performance" talks about
word-addressed machines.  The information in this and other papers helped
shape our implementation.)

    bcase