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From: jewett@hpl-opus.HP.COM (Bob Jewett)
Newsgroups: comp.lsi
Subject: Re: Josephson Junction computers (was: Want to bet he wins a Nobel Prize?)
Message-ID: <2660002@hpl-opus.HP.COM>
Date: Mon, 16-Mar-87 12:22:23 EST
Article-I.D.: hpl-opus.2660002
Posted: Mon Mar 16 12:22:23 1987
Date-Received: Thu, 19-Mar-87 00:45:05 EST
References: <492@cpocd2.UUCP>
Organization: HP Labs, Instrument Tech. Dept.
Lines: 59

> JJ gates can be made to match transmission lines

    Because the currents are ~0.2mA, and voltages about 2mV for impedances of
    about 10 ohms, and power dissipation of roughly 1uW.

> At liquid helium temperatures, it's possible to use superfluid
> effects in the LHe to cool them, allowing 3D stacking of die.

    The present excitement is due to the higher temperature superconductors
    (a thin film has been fabricated at Stanford, Tc=35K) where superfluidity
    doesn't occur.

>    Given a computer that consumes milliwatts

    IBM projected 8 watts for a 370-equivalent with ~3ns cycle time.

> simplified, even with Carnot efficiencies included.

    The typical power multiplier (power_room_temp/power_He) is 2000,
    or 1000 for very efficient refrigerators to 4.2K, giving a projected room
    temperature AC requirement of the hypothetical LHe 370 of 16kW.

> (Note: superconducting wires are still dispersive - at a Terahertz or so).

    IBM was able to maintain ~100ps risetimes from chip to circuit carrier.
    The problem was inductance and crosstalk in the pins to the circuit
    carrier.  This implies a useful inter-chip bandwidth of 3GHz.

> With proper design and close attention to device matching, a JJ circuit
> shouldn't be much harder to design than an NMOS circuit.

    IBM had (and Japan has) a lot of bright poeple working on circuit design.
    None of them has come up with a design that can tolerate a +-50% error in
    junction current levels.

> However, this isn't stopping Fujitsu, who just built a 16 bit ALU slice
> with JJ technology.

    The circuit that Fujitsu reported on at the ISSCC had only 900 gates.
    It was not clear from either the presentation or the Digest paper whether
    they ever got all 900 gates to work on one chip.  Their reported timing
    measurement was (using their more conservative number) 1.7ns for 16 bit
    carry propagation, but this was not measured in the ALU itself.  It was
    measured in a special 36-gate test circuit that duplicated the critical
    delay path.

> But when those schemes hit the wall (and on some problems they will),
> JJs may be the way out.

    IBM dropped JJs when it appeared that there would be further delays and
    the speed advantage over semiconductor circuits would only be a factor
    of 3.  When the project started, that factor was larger than 10.  IBM did
    demonstrate a cross-section model (CSM) of a signal processor.  It ran
    with a 3ns cycle time, including memory fetch time.  The I/O, cooling,
    shielding and interconnect problems all seemed to have been solved.

> Keith Lofstrom

    Bob Jewett   hplabs!jewett