Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watnot!watmath!clyde!rutgers!princeton!allegra!ulysses!sfmag!sfsup!perry From: perry@sfsup.UUCP Newsgroups: comp.sys.amiga Subject: Re: Timing on A2000 vs 1000-add-ons Message-ID: <1310@sfsup.UUCP> Date: Fri, 10-Apr-87 12:30:57 EST Article-I.D.: sfsup.1310 Posted: Fri Apr 10 12:30:57 1987 Date-Received: Sat, 11-Apr-87 21:24:48 EST References: <18261@ucbvax.BERKELEY.EDU> Organization: AT&T-IS, Summit N.J. USA Lines: 36 Summary: Proper Buffering Is Key In article <18261@ucbvax.BERKELEY.EDU>, schoet@ernie.Berkeley.EDU (Steve Schoettler) writes: > If worst case design of peripherals for the A1000 is so bad that > manufacturers could only make 1 or 2 slot card cages, how is it that > now so many vendors can offer 2000-and-1 boxes? > I can understand how a redesign of a circuit board and adding custom > chips can give you more timing flexibility, but how can they do it to the > A1000 without adding wait states? > I have ultimate faith in ASDG; if it can be done, they will do it. > But why were we (at least I was) led to believe by so many hardware > vendors in the past that it couldn't be done? Proper (full spec) buffering allows a reasonably large number of expansion slots to be placed in ONE expansion box. This is what the framers of the Zorro spec envisioned from the start. Current slap-on-the-side-with-uh-oh-pass-thru products DO NOT PROPERLY buffer. You're gonna need proper buffering to allow proper operation. A slap-on-the-side-with-pass-thru product (if one existed which properly buffered the bus) would squander the bus buffering on exactly one board. This means downstream products which would presumably also buffer the bus would begin to incur wait states (slots in a single card rack though do not incur wait states if the containing card rack is the first card rack in the chain - and - to my knowledge no one seriously expects two fully buffered card racks to be plugged into each other and work reliably.). To sum up: Buffering is essential. Buffering more than once leads to wait states downstream. Sots products do not buffer because they are inefficient card racks (they contain only one board) and to buffer properly would mean wait states for products downstream. Card racks are more efficient card racks (like that one?) in that their bus buffering ammortizes over several boards. Also, thanks for the faith. You're right. If it can be done - we can do it. Perry S. Kivolowitz ASDG