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Path: utzoo!utcsri!utgpu!ac
From: ac@gpu.utcs.toronto.edu
Newsgroups: comp.sys.m6809
Subject: OS9 Level II at 1MHz
Message-ID: <1987Apr2.150812.4974@gpu.utcs.toronto.edu>
Date: Thu, 2-Apr-87 15:08:12 EST
Article-I.D.: gpu.1987Apr2.150812.4974
Posted: Thu Apr  2 15:08:12 1987
Date-Received: Sat, 4-Apr-87 11:37:06 EST
Organization: University of Toronto Computing Services
Lines: 24
Checksum: 20143


   I have resolved my problem with running OS9 level 2 at 1MHZ (actually .89).
I eventually found this interesting delay 'loop' in CC3DISK.  The code
looks like this:
l0 lbsr l1
l1 lbsr l2
l2 lbsr l3
l3 rts
It is entered at 'L0'.  In the level I drivers there is one less 'lbsr'
instruction.  If I understand the code correctly, adding the extra lbsr
results in about a twofold increase in the delay time.  Since I'm running
at half the speed I replaced the lbsr at l2 with an rts.  This appears
to make my system work.  I still don't fully understand why this change
is required.  This delay code is called just after storing the write
command into the FDC command register, but before starting a spin loop
waiting for bit $02 of the FDC status register to be set.  I don't
know enough about the FDC to understand the exact nature of the timing
window involved.

-- 

Name:     Mark Acfield (University of Toronto Computing Services)
Path:     ihnp4!utgpu!ac   
Alias:    ac@utoronto.bitnet