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From: root@sbcs.UUCP
Newsgroups: comp.sys.m68k
Subject: Re: Was Re: Recent Motorola ad seen in Byte
Message-ID: <383@sbcs.UUCP>
Date: Tue, 7-Apr-87 16:04:25 EST
Article-I.D.: sbcs.383
Posted: Tue Apr  7 16:04:25 1987
Date-Received: Sat, 11-Apr-87 07:31:59 EST
References: <8704050506.AA25220@cory.Berkeley.EDU>
Organization: Computer Science Dept, SUNY@Stony Brook
Lines: 33

> your talking enough complexity that having the MMU internal or external
> doesn't really make a difference.  Don't get me wrong... I'm all for having

	MMU done internally vs externally DOES make a difference - it is
fairly hard to pipeline an external MMU so that translation/protection
doesn't slow your basic memory cycle time by 25-50%.  Yes, clever RAS/CAS'ing
(ala Sun/Becholsteim) helps, but I want my translation done on CPU
silicon where the system designer can't "forget" the MMU, come up with
non-standard architectures (read custom port of Unix for EVERY machine),
make hardware tradeoffs (e.g. pagesize) in the absence of software
expertise, etc.. 

> 	In terms of the dreaded 68020/80386 wars, and if I took a 
> neutral stance on the speed issue, it all comes down to a preference
> of which instruction set one likes best.  I personally (and this is why

My personal loyalty is solely for the fastest (75%), cheapest (5%),
most standard (20%) silicon at any given point.  Instruction sets are 
nice to talk about, but lets face it, they are really only for compilers 
and compiler writers to worry over.  I hack assembly language (it doesn't 
matter which or how elegant after all these years) on the 20% of the 
programs I write which can't do what I need in C (perhaps 0.1 % of the 
overall code of these programs).  Anyways, with the advent of RISC, the 
days of polynomial instructions, offset@(reg, reg:size) addressing modes 
are numbered.

The whole point of this is merely:  Give me a fast 32 bit programming
environment with translation/protection, and I'll be happy..  With the
386, 29000 (almost), 68030 (almost) out, it doesn't matter whether the 
cover on the chip carrier reads "Motorola", "Intel", "AMD", etc.

					Rick Spanbauer
					SUNY/Stony Brook