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Path: utzoo!utgpu!water!watnot!watcgl!awpaeth
From: awpaeth@watcgl.UUCP
Newsgroups: sci.electronics
Subject: Re: Question about multi-switched lights
Message-ID: <788@watcgl.UUCP>
Date: Thu, 26-Mar-87 11:34:02 EST
Article-I.D.: watcgl.788
Posted: Thu Mar 26 11:34:02 1987
Date-Received: Fri, 27-Mar-87 05:33:53 EST
References: <1922@ihlpl.ATT.COM> <562@puff.WISC.EDU> <3972@fritz.UUCP> <18002@ucbvax.BERKELEY.EDU> <18008@ucbvax.BERKELEY.EDU>
Reply-To: awpaeth@watcgl.UUCP (Alan W. Paeth)
Organization: U. of Waterloo, Ontario
Lines: 49

In article <18008@ucbvax.BERKELEY.EDU> albert@ucbarpa.Berkeley.EDU.UUCP (Anthony Albert) writes:
>Well, I thought about it some more and figured it out. It requires 2 DPDT
>switches.
>
>
>                                        ___
>          ____ \___ _ _ _ _ _ _ _ _ _ __|  \___
>         |                                     |
>_________|                                     |________
>         |_____                                |
>	       \___ _ _ _ _ _ _ _ _ _ ____ \___|
>
>
>This represents 2 DPDT switches connected by 2 wires (_ _ _). To create a
>similar circuit with 3 switches, they'd have to be 4 pole. In general, a
>                                               n-1
>circuit with n switches requires each to have 2    poles.
>
>

I missed the original question - but if it is a matter of turning a light
on or off from any of N switches, then 2P2T switches suffice. The solution is
a circuit which maintains circuit parity, using a "double rail" signalling
convention (lamp current and "signal" are synonomous):

-AC-----. <+ +--> .-----. <+ +--> .            .--- load ------(ground)
           | .             | .         <etc> 
           --.--           --.--   
             . |             . |   
        . <--+ +->.-----. <--+ +->.            .



Each switch is 2P2T wired in a polarity reversing arrangment (the throws
oppose in the diagram, and move together). In one state, the two inputs
pass through to the two outputs, in the other, they reverse roles. At any
stage, the upper (lower) rail carries AC, while the lower (upper) rail is
left floating. For an N switch circuit, the end switches need only be SPDT,
as half the switch is unused. These are termed "three way" switches in
hardware stores. The remaining N-2 intermediate switches need only provide
four external connections. They are sold under the name "four way".

Incidentally, MOS (as opposed to Bipolar) VLSI technology allows one to
build analogous structures very easily. These have merit in doing parity
operations (e.g. the Sum bit in a full adder is the parity of both addends
and the carry in) using "switch" and not "gate" logic, which can often
reduce circuit area and reduce propagation delay.

    /Alan Paeth