Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!mnetor!seismo!lll-lcc!mordor!sri-spam!sri-unix!husc6!harvard!ksr!john!ned
From: ned@john.ksr.com (Kittlitz)
Newsgroups: comp.arch
Subject: Re: AM29000 memory management (was flame)
Message-ID: <93@ksr.UUCP>
Date: Tue, 28-Apr-87 15:08:52 EDT
Article-I.D.: ksr.93
Posted: Tue Apr 28 15:08:52 1987
Date-Received: Thu, 30-Apr-87 02:25:26 EDT
References: <67@bernina.UUCP> <27207@rochester.ARPA> <121@motsj1.UUCP> <342@winchester.UUCP>
Sender: nobody@ksr.UUCP
Reply-To: ned@ksr.UUCP (Kittlitz)
Distribution: world
Organization: Kendall Square Research, Cambridge MA
Lines: 23


How does MIPS TLB load deal with used/modified bits? I assume that
part of the path always executed determines that the bits are in the
correct state. i.e. some of the instructions included in your count
are for is-used-set?, is-this-a-write-well-then-is-modified-set?.

Assuming that these are coded with branch-not-taken being common
(used/modified already has correct value), a multiprocessor still has
to do some kind of exclusivity locking when it diddles the bits.
Got any multi implementation or plans you can talk about? e.g.
how long would THAT sequence be?

Can you describe any special hardware characteristics of the TLB in
greater detail (or is it published)? How about the way you use the TLB
in your UN*X implementation.



-----
disclaimer: generic disclaimer *

* - have you seen advertisements with '*'s, and no footnote?
It's the same with this disclaimer...