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From: daasch@psueea.UUCP
Newsgroups: comp.arch
Subject: Ideas for coprocessor protocol(s)/interface
Message-ID: <411@psueea.UUCP>
Date: Wed, 29-Apr-87 16:18:56 EDT
Article-I.D.: psueea.411
Posted: Wed Apr 29 16:18:56 1987
Date-Received: Sat, 2-May-87 01:40:05 EDT
Distribution: na
Organization: Dept. of Electrical Engineering, Portland State University; Portland OR
Lines: 26


I would be interested in expanding the recent series on "on-chip or 
off-chip MMU" to the coprocessors and the "ideal protocol?"  Here at 
PSU we are working on a IC subsystem (MOSIS CMOS etc.) for supporting 
the 020 protocol.  I think it is fair to say that it is based on a 
notion that a coprocessor is a special purpose peripheral that shares code 
(operands etc. are inline with the 020 instructions).  I don't know 
details but I believe Intel doesn't use this scheme with the 386.  
Questions to get started could be: 

1) How is the coprocessor limited (both hardware and software )
by the protocol?

2) Is there a reasonable sized "set of protocols" that would support
a broad spectrum of coprocessors?

3) What coprocessors are going to be needed?  This would get away from
rehashing FPU, MMU and the like.

Reply to ...!tektronix!psu-cs!psueea!daasch or post and I'll gladly
collect an archive.

Thanks,
Rob D.
...!tektronix!psu-cs!psueea!daasch
daasch@portland.csnet