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From: ram@nucsrl.UUCP
Newsgroups: comp.arch
Subject: Japanese 32-bit CPUs
Message-ID: <3810030@nucsrl.UUCP>
Date: Sun, 3-May-87 02:59:45 EDT
Article-I.D.: nucsrl.3810030
Posted: Sun May  3 02:59:45 1987
Date-Received: Tue, 5-May-87 01:24:16 EDT
Organization: Northwestern U, Evanston IL, USA
Lines: 70


    The Japanese are tagging along with 32 bit machines:

    This is some info for the interested:

    1. From Electronics of Apr 16.

	Japan's first microprocessor with 32-bit data and address buses
	runs at a maximum rate of 6.6 MIPS - 4 MIPS is typical of 32-bit
	chips(Roger,Brian,John - smile here).  Fabricated in 1.5um CMOS,
	the NEC V70 has a dynamic bus sizing that enables it to match
	input/output with 8,16, and 32 bit buses.  Its TRON (we are entering
	space age) OS will make it shine in real-time control and robot
	applications.  The 20MHz V70 also incorporates FP(!!) facilities
	on-chip and has function redundancy monitor for fault-tolerant
	computing.  Sample prices of the device is $687.52.  Prices
	will be lower for production quantities.

    The spec on FP on-chip is rather confusing.  I doubt if a hardware
    FP unit exists on chip.  ANy clarifications?  Also, will it be
    compatible with iAPX386 :-).

    2.  From the same magazine:

	Japan's NTT has world's fastest Lisp Processor.  

	The machine called ELIS is a dual-processor machine, one 68010 used
	as a frontend processor and another micro-programmed Lisp processor.
	From the diagram, I see an FP accelerator included with the machine.
	Claimed performance: 1 M basic lisp instructions/sec.  [What the
	hell is basic lisp instruction? (car '(a b c))? -artificialstone :-)]
	Has 128M of mem, multiple paradigm language - Tao (has flavors of 
	Common lisp, prolog and smalltalk).  The micro-program control store is
	64K of 64 bit words and 1K register stack (of 32 bit size).
	The 68010s softwareis written in C and for the Lisp processor in
	Tao.  I lost my data sheets/info on TI's Lisp processor to compare
	these two.  Anybody care to.

    3.  Mitsubishi's 32 bit mP for their TRON project.

	Some details

	    1. No TLB
	    2. RISCy (at least adhering to lean cycles, fixed format
	       simple instructions).
	    3. 1mM CMOS
	    4. 25-33 MHz
	    5. 5 stage pipeline.
	    6. Instruction queue size - 16 bytes
	    7. 3 bus ALU
	    8. Branch prediction ideas seem to be modelled after
	       Hennesey's & A.J. Smith's work.
            9. "A high speed memory for saving contexts, can also
	       be incorporated".

    
    One cavaet about complex CPUs.  [Notice how the big semiconductor
    manufacturers have started anouncing like GM/FORD/CHRYSLER (1988 car
    in 1987, 1989 car in 1988 - wonder what type of calendar they use) with
    chip of the future to-day.].  Judging by AMD and NSC announcements, it 
    takes at least 1 yr for Si to be available after initial announcement and 
    given the complexity of these chips, it takes at least 1 year for the bugs
    to be weeded out before the chip hardware becomes stable (386, 32X32). 
    Do we need more complex designs on a single wafer or go for "small is 
    beautiful". 

-------------------
Renu Raman				UUCP:...ihnp4!nucsrl!ram
1410 Chicago Ave., #505			ARPA:ram@eecs.nwu.edu 
Evanston  IL  60201			AT&T:(312)-869-4276