Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!seismo!ll-xn!mit-eddie!husc6!necntc!pec From: pec@necntc.NEC.COM (Paul Cohen) Newsgroups: comp.arch Subject: Re: Japanese 32-bit CPUs Message-ID: <3910@necntc.NEC.COM> Date: Mon, 4-May-87 11:48:39 EDT Article-I.D.: necntc.3910 Posted: Mon May 4 11:48:39 1987 Date-Received: Tue, 5-May-87 01:46:11 EDT References: <3810030@nucsrl.UUCP> Reply-To: pec@necntc.UUCP (Paul Cohen) Organization: NEC Electronics Inc. Natick, MA 01760 Lines: 62 > This is some info for the interested: > > 1. From Electronics of Apr 16. > > Japan's first microprocessor with 32-bit data and address buses > runs at a maximum rate of 6.6 MIPS - 4 MIPS is typical of 32-bit > chips(Roger,Brian,John - smile here). Fabricated in 1.5um CMOS, > the NEC V70 has a dynamic bus sizing that enables it to match > input/output with 8,16, and 32 bit buses. Its TRON (we are entering > space age) OS will make it shine in real-time control and robot > applications. The 20MHz V70 also incorporates FP(!!) facilities > on-chip and has function redundancy monitor for fault-tolerant > computing. Sample prices of the device is $687.52. Prices > will be lower for production quantities. > > The spec on FP on-chip is rather confusing. I doubt if a hardware > FP unit exists on chip. ANy clarifications? Also, will it be > compatible with iAPX386 :-). > The V70's floating point is implemented not as a separate unit, but with additional microcode. There are some refinements of the ALU to facilitate this, such as a 64 bit barrel shifter. 32 and 64-bit IEEE standard basic arithmetic functions (add, subtract, multiply, divide, convert) are supported on-chip. A separate floating point unit for 80 bit operations and specialized functions such as transcendental and matrix operations will be available in the near future. The V70 is * * * N O T * * * 386 compatible. It has thirty-two general purpose 32-bit registers, an orthogonal instruction set and generally a much cleaner architecture that is not hampered by decisions made years ago for 16-bit machines (I am talking about native mode V70: it does have an emulation mode so that it can execute V30 machine code (a superset of 80186 code)). The V70 has an on-chip MMU so that virtual memory accesses can take place in two clocks. The processor also supports bit addressing and has some interesting (bit, byte and half-word) string instructions. The V70 is identical, except for bus interface, with the V60. You can get a V60 programmer's reference manual and a V70 datasheet by calling 1-800-NEC-ELEC (California) 1-800-NEC-ELE1 (Outside California) These telephones are supported only during west coast working hours. > One cavaet about complex CPUs. [Notice how the big semiconductor > manufacturers have started anouncing like GM/FORD/CHRYSLER (1988 car > in 1987, 1989 car in 1988 - wonder what type of calendar they use) with > chip of the future to-day.]. Judging by AMD and NSC announcements, it > takes at least 1 yr for Si to be available after initial announcement and > given the complexity of these chips, it takes at least 1 year for the bugs > to be weeded out before the chip hardware becomes stable (386, 32X32). > Do we need more complex designs on a single wafer or go for "small is > beautiful". > V70 silicon already exists and is fairly functional (after all, the V70 is not much different from the V60). Customer samples of the V70 should be available in the third quarter of this year. If you are seriously interested I can arrange for V60 samples now.